1. Field of the Present Invention
The present invention generally relates to the field of integrated circuits and more particularly to the interfaces in an integrated circuit that enable communication with another integrated circuit.
2. History of Related Art
In high speed data processing systems employing multiple integrated circuits (modules or chips), inter-device communication is facilitated through chip interfaces that typically include buffering and driver circuitry. These interfaces typically compensate for static manufacturing and design variables. These static variables include silicon doping levels, electrical line length and width variations, both within a chip and on a printed circuit board (PCB) to which the chip is attached, inherent design tolerances, and the like. As their name implies, static variables are typically fixed after manufacturing and remain generally constant over the life of the system.
Systems and methods to compensate for the effect of static variables are known. Compensation for static variables typically occurs at system power-on. During a static variable compensation process, signals on an interface in the system are adjusted on the receive chip's silicon to optimize performance. Interfaces capable of being tuned in this manner are referred to as tunable interfaces.
An example tunable interface process from the assignee of the present application is referred to as the Initialization Alignment Procedure (IAP). The IAP is described, for example, in a co-pending, commonly owned, U.S. patent application: Dreps et al., Elastic Interface Apparatus and Method Thereof, Ser. No. 09/961,506, filed Sep. 24, 2001 [hereinafter “Dreps”]. The IAP is a sub-process within the system power-on procedure, which typically can take several seconds or minutes to complete.
As microprocessor clock frequencies continue to increase, so must the clocking frequencies of inter-chip busses, such as the busses between the microprocessor an external cache memory, system memory, and I/O devices if the processor is to be fully supplied with instructions and data. To achieve high speed busses, aggressive interface device designs must be incorporated on the microprocessor and support chips. Moreover, compensation for static variables is just the beginning. Transient environmental changes in an operating computer system, such as changes in temperature and voltage seen by the chips transmitting and receiving data via a bus interface, may cause the timing of data being transmitted across that bus interface to drift.
In the past, interface designs simply increased or relaxed their operating margins to account for this dynamic interface variation. Increased operating margin, unfortunately, results in slower interface speeds because the transient drift may account for as much as half of the data valid window margins. It would therefore be desirable to implement an integrated circuit device interface with the ability to compensate for transient or dynamic drift so that maximum performance over the interface is achievable.
A prior effort to achieve dynamic recalibration described in Floyd, et al., Data Processing System and Method with Dynamic Idle for Tunable Interface Calibration, U.S. patent application Ser. No. 09/946,217 filed Sep. 5, 2001 [hereinafter “Floyd”] incorporated a periodic system idle to recalibrate the interface. While this approach achieves dynamic recalibration, the periodic system idle approach has drawbacks. First, if a system interface does drift out of calibration, it will continue to operate out of calibration until the next periodic recalibration takes place. In the interim, the system may experience correctable errors or even permanent data loss. While this problem can be lessened by increasing the periodic calibration frequency, such a solution would decrease overall system performance since the calibration consumes the bandwidth of the interface and requires an overhead routine to protect the system's data from corruption. Second, the periodic calibration may occur at a time when the interface is within specification thereby unnecessarily incurring the calibration procedure overhead. Accordingly, it would be desirable to implement a system that implemented dynamic calibration of an interface that did not suffer from the drawbacks of the periodic calibration implementation.